1. Field of the Invention
This invention relates generally to coded signal processing channels for converting an analog transducer signal into a series of digital signals corresponding to coded binary data and particularly to a digital timing recovery circuit for producing an instantaneous clock phase error signal in a (1,7)ML channel.
2. Discussion of the Related Art
A magnetic or optical data recording and playback channel is designed to accept data for storage and to later deliver the same on retrieval demand without errors or unreasonable access delay. Self-clocking modulation codes are employed to ensure an adequate minimum rate of signal transitions for clock synchronization during data retrieval without exceeding the maximum transition storage density of the magnetic or optical medium used to store the data. Such modulation codes include run-length-limiting (RLL) codes that represent a one-to-one mapping of binary data into a constrained binary sequence that is then recorded on the recording medium as a series of magnetic polarity reversals or optical "transitions".
Increases in medium recording density impose heavy demands on the playback signal detection process in a magnetic or optical recording channel. In commonly assigned U.S. Pat. No. 4,945,538, fully incorporated herein by this reference, Patel discloses a (1,7)ML sequence detector that employs a state-dependent sequence detection process to compute appropriate functional expressions of digital sample values over a detection window wider than the usual single-bit window employed in classical RLL decoders. Because Patel's (1,7)ML recovery process can be programmed to adjust decision thresholds, the threshold constants can be modified for different tracks or bands of tracks in a magnetic or optical disk file to optimize performance over every track in the file.
In commonly assigned U.S. Pat. Nos. 5,282,216 and 5,291,500, both fully incorporated herein by this reference, Patel et al. describe improvements to and extensions of Patel's (1,7)ML channel signal processing method. The improved channel includes an analog-to-digital converter (ADC) that receives a clock signal from a phase-locked loop (PLL) oscillator and accordingly produces digitized sample values of the analog playback signal at successive sample times. To eliminate clock phase error, unwanted differential delay between the channel clock signal and the self-clocking analog playback signal is removed by a discrete delay element that allows manual adjustment of delays in small increments.
In commonly assigned U.S. Pat. No. 5,266,850, fully incorporated herein by this reference, Au et al. disclose a method and circuitry for automatically adjusting the delay setting of the Patel et al. delay element to ensure phase synchronization of the clock signal with the analog signal at the ADC element of the channel. Although the Au et al. circuitry is quite practical for use in a constant data rate magnetic or optical storage device channel, the delay element must be frequently adjusted to a new setting for each zone in a constant density (Zone Band Recorded or ZBR) storage device. This requirement for continual resynchronization of the clock phase reduces the efficiency of the Au et al. Delay Trim circuitry, unfavorably affecting either the channel hardware design or the requisite track formatting process or both.
There is accordingly a clearly-felt need in the art for a more efficient timing recovery procedure suitable for application to ZBR device channels. In commonly-assigned U.S. Pat. No. 5,295,128, Hutchins et al., disclose a useful digital data clock control loop for reconstructing the asynchronous data clock in a ZBR or other data processing channel. Hutchins et al. disclose and claim a discrete clock control loop applied in a sampled data system in which phase adjustments are made on a recursively weighted moving sum of phase errors accumulated over several sample periods on the digital side of the loop. Although their continuing clock reconstruction process is well-suited to ZBR channels, Hutchins et al. consider an asynchronous clock and thus neither consider nor suggest any means for producing an instantaneous phase error correction signal for the direct phase adjustment of the synchronous waveform sampling means.
Although the methods and circuits described in the cited commonly-assigned U.S. patents operate satisfactorily, the unresolved problems and deficiencies associated with automatic clock delay trimming in a ZBR storage device channel are clearly felt in the art and are resolved by this invention in the manner described below.